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    • 专利摘要:
    The invention relates to a device for transferring chips from a source substrate to a destination substrate, comprising: a source substrate (100) having a lower face and an upper face; and a plurality of elementary chips (150) arranged on the upper face of the source substrate, in which each elementary chip (150) is suspended above the source substrate (100) by at least one breakable mechanical fastener (120), said at minus a breakable mechanical fastener having a lower face fixed to the upper face of the source substrate (100) and an upper face fixed to the lower face of the chip (150).
    公开号:FR3082998A1
    申请号:FR1855672
    申请日:2018-06-25
    公开日:2019-12-27
    发明作者:Stephane Caplet；Laurent Mollard
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    DEVICE AND METHODS FOR TRANSFERRING CHIPS FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATE
    Field
    The present application relates to the field of techniques for transferring chips from a source substrate to a destination substrate, for the manufacture of electronic or optoelectronic devices, and in particular for the manufacture of an image display device comprising a plurality elementary electronic chips mounted on the same transfer substrate. The present application relates more particularly to a device for transferring chips from a source substrate to a destination substrate, a method of manufacturing such a device, and a method for transferring chips from a source substrate to a destination substrate at by means of such a device.
    Presentation of the prior art
    It has already been proposed, in French patent application No. 1561421 filed on November 26, 2015, a method of manufacturing an image display device comprising a plurality of elementary electronic chips arranged in a matrix on the same substrate. postponement. According to this process, the chips and the transfer substrate are produced separately. Each elementary chip comprises a stack of a light-emitting diode (LED) and a control circuit of the LED. The control circuit includes
    B16534 - DD18354 a connection face opposite the LED, comprising a plurality of electrical connection pads intended to be connected to the transfer substrate for controlling the chip. The transfer substrate for its part comprises a connection face comprising, for each chip, a plurality of electrical connection pads intended to be connected respectively to the electrical connection pads of the chip. The chips are then transferred onto the transfer substrate, connection faces facing the connection face of the transfer substrate, and fixed on the transfer substrate so as to connect the electrical connection pads of each chip to the corresponding electrical connection pads of the transfer substrate.
    During the implementation of the transfer step, the individual elementary chips are placed on a support substrate, or source substrate, each chip being fixed to the source substrate by its face opposite to its electrical connection face. The chips are then positioned facing the corresponding connection areas of the transfer substrate, or destination substrate, connection faces of the chips facing the connection face of the destination substrate, using the source substrate as a handle. The chips are then fixed on the destination substrate so as to bring the electrical connection pads of each chip into contact with the corresponding electrical connection pads of the destination substrate. The chips are then detached from the source substrate, and the latter is removed.
    In practice, the pitch of the elementary chips on the source substrate can be less than the pitch of the final device, that is to say the pitch of the chips on the destination substrate. In this case, provision is made, at each transfer step, to transfer only part of the chips from the source substrate to the destination substrate, in step with the source substrate, then, if necessary, to shift the source substrate with the remaining chips to transfer another part of the chips, and so on until
    B16534 - DD18354 all the chips of the display device have been fixed on the destination substrate.
    A difficulty which arises in such a method is that the energy of adhesion between the elementary chips and the source substrate must be precisely controlled. In particular, the adhesion energy between the elementary chips and the source substrate must be high enough to keep the chips in place when the chips are positioned facing the corresponding receiving areas of the destination substrate, but sufficiently low so that, once fixed to the destination substrate, the chips detach from the source substrate when the latter is removed.
    Controlling the adhesion energy between the elementary chips and the source substrate in a precise and reproducible manner is difficult to carry out, which poses practical problems during the manufacture of the display device. This difficulty is further accentuated when it is desired to be able to detach the chips from the source substrate selectively in order to effect a change of pitch between the source substrate and the destination substrate as described above.
    More generally, this problem can arise in other application fields requiring the transfer of elementary chips from a source substrate to a destination substrate.
    International patent application WO2015 / 193435 describes a device and a method for transferring micro-objects such as electronic chips from a source substrate to a destination substrate. In this document, the micro-objects are connected to the source substrate by breakable mechanical fasteners intended to break when a predetermined mechanical stress is applied to them. The micro-objects are first removed from the source substrate by means of an intermediate transfer substrate of the elastomeric film type (causing the breakable ties to break), then transferred to the destination substrate by means of the intermediate transfer substrate. The solution proposed in this document however has various drawbacks. In particular, a drawback is that the breakable mechanical fasteners linking the
    B16534 - DD18354 micro-objects with the source substrate occupy a relatively large surface on the source substrate, which restricts the surface density of micro-objects that can be provided on the source substrate. In addition, this document does not describe the making of electrical connections between the micro-objects and the source substrate. Another drawback is linked to the use of an intermediate transfer substrate, which makes the implementation of the transfer operation relatively complex (with in particular the risk of degrading the layers in contact with the transfer tool).
    It would be desirable to be able to have a solution making it possible to transfer chips from a source substrate to a destination substrate, this solution at least partially overcoming one or more of the drawbacks of known solutions.
    In particular, it would be desirable to have a transfer solution suitable for the manufacture of a display device of the type described in the French patent application No. 1561421 mentioned above.
    summary
    Thus, one embodiment provides a device for transferring chips from a source substrate to a destination substrate, comprising:
    a source substrate having a lower face and an upper face; and a plurality of elementary chips arranged on the upper face of the source substrate, in which each elementary chip is suspended above the source substrate by at least one breakable mechanical fastener, said at least one breakable mechanical fastener having a lower face fixed to the upper face of the source substrate and an upper face fixed to the lower face of the chip.
    According to one embodiment, for each chip, said at least one breakable mechanical fastener connecting the chip to the source substrate is located entirely under the chip.
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    According to one embodiment, for each chip, said at least one breakable mechanical fastener connecting the chip to the source substrate is located partly only under the chip.
    According to one embodiment, for each elementary chip, only part of the lower face of the chip is in contact with said at least one breakable mechanical fastener, the remaining part of the lower face of the chip being separated from the upper face of the source substrate by a region free of any solid material.
    According to one embodiment, each elementary chip comprises one or more terminals for electrical connection to an external device arranged on the side of its face opposite the source substrate.
    According to one embodiment, each elementary chip further comprises one or more terminals for electrical connection to an external device arranged on the side of its face facing the source substrate.
    According to one embodiment, the upper face of the source substrate has a surface roughness greater than 5 nm.
    According to one embodiment, each elementary chip comprises an LED.
    According to one embodiment, each elementary chip comprises a stack of an LED and of an elementary LED control circuit, the elementary control circuit being arranged on the side of the LED opposite the source substrate.
    According to one embodiment, each elementary chip is a wavelength conversion element.
    Another embodiment provides a method of manufacturing a device as defined above, comprising the following successive steps:
    a) forming on the upper face of the source substrate a first stack comprising an alternation of at least one permanent solid layer and at least one sacrificial layer so as to define the breakable mechanical attachments of the device;
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    b) adding on the upper face of the first stack a functional layer;
    c) forming singling trenches crossing the functional layer and delimiting the elementary chips of the device; and
    d) etching said at least one sacrificial layer of the bonding stack without removing said at least one permanent solid layer.
    Another embodiment provides a method of manufacturing a device as defined above, comprising the following successive steps:
    a) forming a functional layer on one face of a temporary support substrate;
    b) forming, on the face of the functional layer opposite the temporary support substrate, a bonding stack comprising an alternation of at least one permanent solid layer and at least one sacrificial layer so as to define the breakable mechanical attachments of the device;
    c) attaching the assembly comprising the temporary support substrate, the functional layer and the bonding stack to the upper face of the source substrate, so that the temporary support substrate is disposed on the side of the bonding stack opposite to the source substrate, then remove the temporary support substrate;
    d) forming singling trenches crossing the functional layer and delimiting the elementary chips of the device; and
    e) etching said at least one sacrificial layer of the bonding stack without removing said at least one permanent solid layer.
    According to one embodiment, said at least one permanent solid layer is made of silicon oxide, and said at least one sacrificial layer is made of polycrystalline silicon.
    According to one embodiment, the step of etching said at least one sacrificial layer of the stack of
    B16534 - DD18354 bonding without removing said at least one permanent solid layer is produced by etching based on xenon di-fluoride.
    Another embodiment provides a method of transferring elementary chips from a source substrate to a destination substrate by means of a device as defined above, comprising the following successive steps:
    position the elementary chips in relation to corresponding transfer zones of the destination substrate by using the source substrate as a handle;
    fix the elementary chips on the destination substrate by their face opposite to the source substrate; and moving the source substrate away from the destination substrate so as to break the breakable mechanical fasteners connecting to the source substrate the elementary chips now secured to the destination substrate.
    According to one embodiment, the step of fixing the elementary chips on the destination substrate comprises the electrical connection of electrical connection terminals previously formed on the face of the elementary chips opposite the source substrate, to corresponding electrical connection terminals of the destination substrate .
    According to one embodiment, the pitch of the elementary chips on the source substrate is less than the pitch of the elementary chips on the destination substrate.
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures, among which:
    Figures IA, IB, IC, ID, IE, 1F and IG are sectional views illustrating steps of an example of an embodiment of a method of manufacturing a device for transferring chips of a source substrate on a destination substrate;
    Figure 2 is a partial perspective view of the device produced by the method of Figures IA to IG;
    B16534 - DD18354 Figures 3A, 3B, 3C, 3D, 3E, 3F and 3G are sectional views illustrating steps of an example of another embodiment of a method of manufacturing a device for the transfer chips from a source substrate on a destination substrate; and FIGS. 4A, 4B and 4C are sectional views illustrating steps of an example of an embodiment of a method for transferring chips from a source substrate to a destination substrate by means of a device produced by the process of Figures IA to IG or by the process of Figures 3A to 3G. detailed description
    The same elements have been designated by the same references in the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements useful for understanding the described embodiments have been shown and are detailed. In particular, the structures and the functionalities of the elementary chips which it is sought to be able to transfer from a source substrate to a destination substrate have not been detailed, the embodiments described being compatible with all or most of the structures and known chip functionality. In addition, the structures and functions of the electronic or optoelectronic devices that one seeks to achieve have not been detailed, the embodiments described being compatible with the production of any device requiring for its manufacture the postponement of one or several chips from a source substrate to a destination substrate.
    It will be noted that by chip, we mean here a microstructure in thin layers, for example a structure of which all the horizontal dimensions (that is to say the dimensions in top view) are less than 5 mm, for example less than 1 mm, for example less than 0.5 mm, for example less than 0.1 mm, for example less than 50 pm, and whose thickness is less than 1 mm, for example less than 0.5 mm, for example less 0.1 mm, for example less than 50 µm. Within the meaning of
    B16534 - DD18354 In the present description, a chip can comprise one or more active and / or passive electronic components, and / or one or more optoelectronic components, and / or one or more optical components.
    In the following description, when referring to qualifiers of absolute position, such as the terms forward, backward, up, down, left, right, etc., or relative, such as the terms above, below, upper , lower, etc., or to orientation qualifiers, such as the terms horizontal, vertical, etc., reference is made to the orientation of the figures, it being understood that, in practice, the structures described can be oriented differently . Unless specified otherwise, the expressions approximately, appreciably, and of the order of mean to the nearest 10%, preferably to the nearest 5%.
    Provision is made here for making an assembly comprising a source substrate having a lower face and an upper face, and a plurality of elementary chips disposed on the upper face of the source substrate, each chip being held suspended above the source substrate by at least one breakable mechanical tie or link. According to one aspect of an embodiment, each breakable mechanical fastener has a lower face fixed to the upper face of the source substrate and an upper face fixed to the lower face of the corresponding chip. Thus, each breakable mechanical fastener is located at least partly under (directly below) the corresponding chip. This is a difference compared to the solutions described in the above-mentioned international patent application WO2015 / 193435, in which the breakable mechanical fasteners are located next to the chips and fixed to the lateral faces of the chips, which limits the surface density of chips (number chips per unit area) may be provided on the upper face of the source substrate. In a particularly advantageous embodiment, each breakable mechanical fastener is located entirely under the corresponding chip, so as to
    B16534 - DD18354 maximize the surface density of chips that can be provided on the upper face of the source substrate.
    Figures IA, IB, IC, ID, IE, 1F and IG are schematic and partial sectional views illustrating successive steps of an example of an embodiment of a method of manufacturing a device for the transfer chips from a source substrate to a destination substrate. More particularly, FIGS. 1A to 1G illustrate steps of a method of manufacturing a device comprising a source substrate 100, and a plurality of elementary chips 150, for example identical or similar, suspended above the upper face of the substrate 100, each chip 150 being connected to the substrate 100 by at least one breakable tie (two in the example of FIGS. 1A to 1G) connecting the upper face of the source substrate 100 to the lower face of the chip 150. For the sake of simplification , a single chip 150, as well as the corresponding portion of the substrate 100, are shown in FIGS. 1A to 1G, it being understood that, in practice, a large number of chips 150 can be formed simultaneously on the upper face of the substrate 100.
    FIG. 1A illustrates a step of depositing, on the upper face of the source substrate 100, for example a silicon substrate, a protective layer 102, for example made of silicon oxide. The layer 102 is for example in contact with the upper face of the substrate 100. By way of example, the layer 102 extends continuously over the entire upper surface of the substrate 100. By way of example, the layer 102 has a thickness between 0.1 and 1 μm.
    FIG. 1A also illustrates a step of depositing a sacrificial layer 104 on the upper face of the protective layer 102, for example in contact with the upper face of the protective layer 102. The layer 104 is made of an etchable material selectively with respect to the material of layer 102. By way of example, layer 104 is made of polycrystalline silicon. The layer 104 has for example a thickness between 100 and 500 nm. Layer 104 includes openings
    B16534 - DD18354 through 105 leading to the upper face of the protective layer 102, defining areas for anchoring breakable mechanical fasteners to the upper face of the protective layer 102. In this example, for each elementary chip 150, two openings 105 disjointed are formed in the sacrificial layer 104, corresponding respectively to the anchoring zones of the two breakable mechanical fasteners connecting the chip 150 to the substrate 100. For example, the sacrificial layer is first deposited continuously over the entire upper surface of the protective layer 102, then removed locally by photolithography and etching to form the openings 105. The openings 105 are for example placed under the (perpendicular to) future chips 150 of the device. By way of example, for each chip 150 of the device, the openings 105 are in the form of two parallel strips, for example rectilinear, arranged in two distinct halves of the chip 150. By way of example, each opening 105 has a length (not visible in FIG. IA) substantially equal to the horizontal dimension of the chip 150 in the longitudinal direction of the strip. Each opening 105 has for example a width of between 0.1 and 10 μm, for example between 0.2 and 2 μm.
    FIG. 1B illustrates a step of depositing, on and in contact with the upper face of the sacrificial layer 104, a layer 106 of a material such that the material of the layer 104 is selectively etchable with respect to the materials of the layers 102 and 106. For example, layer 106 is made of the same material as layer 102. Layer 106 is deposited on a thickness greater than that of sacrificial layer 104, so as to completely fill the openings 105 beforehand formed in the sacrificial layer 104. The layer 106 can then be planarized, for example by chemical mechanical polishing (CMP), so that a non-zero thickness of the layer 106 remains above the upper face of the sacrificial layer 104 at the end of the planarization stage. For example, at the end of the planarization step, the thickness of
    B16534 - DD18354 layer 106 above the upper face of sacrificial layer 104 is between 50 and 500 nm, for example between 100 and 200 nm.
    In this example, the breakable mechanical fasteners connecting the chips 150 to the substrate 100 are formed in the layer 106. The layer 106 comprises, for each chip 150, one or more through openings 107 opening onto the upper face of the sacrificial layer 104 and delimiting at least partially the breakable mechanical fastener (s) intended to connect the chip 150 to the substrate 100. In the example shown, for each chip 150, the layer 106 comprises two disjointed through openings 107 having, in top view, the form of bands rectilinear parallel to the openings 105 previously formed in the layer 104 (Figure IA). More particularly, in this example, seen from above, the two openings 107 are arranged between the two openings 105, for example respectively juxtaposed with the two openings 105. By way of example, each opening 107 has a length greater than or equal to the dimension horizontal of the chip 150 in the longitudinal direction of the strip. Each opening 107 has for example a width of between 0.05 and 10 μm, for example between 0.1 and 1 μm. By way of example, the layer 106 is first deposited continuously over the entire surface of the structure obtained at the end of the steps of FIG. IA, then removed locally by photolithography and etching to form the openings 107.
    FIG. 1C illustrates a step of depositing a second sacrificial layer 108 on and in contact with the upper face of the layer 106. The layer 108 is made of a material such that the layer 108 is selectively etchable with respect to the layers 102 and 106 As an example, the layer 108 is made of the same material as the layer 104. The thickness of the layer 108 is greater than the thickness of the layer 106 above the sacrificial layer 104, so that the layer 108 completely fills the openings 107 previously formed in layer 106
    B16534 - DD18354 (Figure IB). By way of example, the thickness of the layer 108 is between 100 and 500 nm.
    The layer 108 is for example deposited on the entire upper surface of the structure obtained at the end of the steps of FIGS. IA and IB, then removed locally, for example by photolithography and etching, to define areas 109 for anchoring the mechanical fasteners breakable with a chip 150. More particularly, in this example, each anchoring zone 109 is arranged, in top view, at a distance from an opening 105 (FIG. 1A) previously formed in the lower sacrificial layer 104 (this is ie not juxtaposed with an opening 105), on the side of the opening 105 opposite the opening 107 (FIG. 1B) previously formed in the layer 106. In the example shown, the layer 108 is further removed in view of a central part 111 of the chip situated, in top view, between the two openings 107 previously formed in the layer 106.
    FIG. 1D illustrates a step of depositing an upper protective layer 112 on and in contact with the upper face of the structure obtained at the end of the steps of FIGS. IA, IB and IC. The layer 112 extends over the entire upper surface of the structure, that is to say on and in contact with the upper face of the layer 108 and on and in contact with the upper face of the layer 106 in the regions 109 and 111 in which the layer 108 has been removed. The layer 112 is made of a material such that the layers 104 and 108 are selectively etchable with respect to the layer 112. By way of example, the layer 112 is made of the same material as the layer 102 or as the layer 106. The layer 112 is deposited on a thickness greater than that of the sacrificial layer 108, so as to completely fill the openings 109 and 111 previously formed in the layer 108. The layer 112 can then be planarized, for example by chemical mechanical polishing (CMP) . By way of example, at the end of the planarization step, a non-zero thickness of the layer 112 remains above the upper face of the
    B16534 - DD18354 sacrificial layer 108, for example a thickness between 50 nm and 5 pm, for example between 100 nm and 1 pm.
    At this stage, breakable mechanical fasteners 120 of the device are defined. More particularly, each breakable mechanical fastener 120 includes:
    - At an opening 105 formed in the sacrificial layer 104 (FIG. 1A), a first portion 120a of the layer 106 whose lower face is in contact with the upper face of the lower protective layer 102, and whose face upper is separated from the upper protective layer 112 by the sacrificial layer 108;
    - At an opening 109 formed in the sacrificial layer 108 (FIG. 1C), a second portion 120b of the layer 106, the upper face of which is in contact with the lower face of the upper protective layer 112 and the lower face of which is separated from the lower protective layer 102 by the sacrificial layer 102; and between the opening 105 and the opening 109, a third portion 120c of the layer 106 extending horizontally from a side edge of the first portion 120a to a side edge of the second portion 120b.
    The rupture zone of each breakable mechanical fastener 120 corresponds for example to its horizontal portion 120c, or to the junction between its horizontal portion 120c and its vertical portion 120a. The energy to be applied to break the fasteners 120 can be precisely controlled by adapting the dimensioning of the fasteners, and in particular the thickness of the layer 106 and the dimensions of the horizontal portion 120c of the fastener.
    A normalization heat treatment can optionally be provided after the upper protective layer 112 has been produced, for example annealing at a temperature of the order of 1000 ° C. with a duration of between 0.5 and 2 hours, for example of the order of 1 hour, or annealing at a temperature of the order of 1200 ° C. with a duration of between 1 and 10 seconds, for example of the order of 3 seconds.
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    FIG. 1E illustrates a step of making the elementary chips 150 on the upper face of the protective layer 112. FIG. 1E more particularly illustrates a step of transferring a functional layer 130 on the upper face of the protective layer 112, and for producing the elementary chips 150 in and / or on the functional layer 130. The production of the elementary chips 150 is not detailed, the solutions proposed being compatible with most of the usual structures of elementary chips.
    For example, the layer 130 is a silicon layer, the elementary chips 150 being integrated circuit chips produced in and on the silicon layer 130, for example in CMOS technology.
    In another exemplary embodiment, the layer 130 is a layer of a III-V semiconductor material, for example gallium nitride, the elementary chips 150 being light-emitting diodes produced in and on the layer 130.
    In another exemplary embodiment, the layer 130 is a silicon layer, elementary chips 150 being of the cell PV performed in and on the layer of silicon 130.
    In the above-mentioned examples, each elementary chip 150 may comprise, on its upper face, that is to say on its face opposite to the source substrate 100, one or more terminals 132 for electrical connection of the chip to an external device (two terminals 132 in the example shown), for example in the form of metal pads flush with the upper face of the chips 150. In the example shown, the layer 130 is coated, on the side of its upper face, with an insulating layer 131 , for example made of silicon oxide, the metal pads 132 being arranged in openings formed in the insulating layer 131.
    FIG. 1E further illustrates an optional step of forming conductive microstructures 134 on the upper face of the electrical connection terminals 132, in order to facilitate the implementation of a subsequent step of fixing and
    B16534 - DD18354 for electrical connection of the chips to an external device. By way of example, the microstructures 134 are metallic microtubes, for example made of tungsten, formed by a process of the type described in patent application US2011 / 094789. As a variant, the microstructures 132 are microtips of the type described in patent application US2008 / 190655.
    In the aforementioned examples, each elementary chip can also comprise, on its lower face, that is to say on its face facing the source substrate 100, one or more terminals (not visible in the figures) for electrical connection of the chip 150 to an external device, for example in the form of metal pads flush with the underside of the chip.
    As an alternative embodiment, the layer 130 is a wavelength conversion layer, for example a phosphor layer, or a layer of a matrix comprising quantum dots, or a stack of multiple quantum wells, the chips elementary 150 then being color conversion elements. In this case, the elementary chips 150 may not include an electrical connection terminal. More generally, in the case where the elementary chips 150 only comprise passive optical components, the latter may not include an electrical connection terminal.
    During the step of transferring the functional layer 130 onto the upper face of the upper protective layer 112, the lower face of the layer 130 can be fixed to the upper face of the layer 112, optionally by means of one or more intermediate layers, for example by molecular bonding, by thermocompression, or by any other suitable fixing method.
    FIG. 1F illustrates a step of etching, from the upper face of the assembly obtained at the end of the steps of FIGS. 1A to 1E, trenches 140 for singularizing the elementary chips 150. More particularly, in the example shown, the trenches 140 extend vertically from the
    B16534 - DD18354 upper face of the assembly, pass entirely through the functional layer 130 and the upper protective layer 112, and lead to the upper face of the sacrificial layer 104. The trenches 140 completely surround each elementary chip 150 of the assembly, so as to separate the elementary chips from each other. The trenches 140 are for example produced by reactive ion etching (RIE).
    Figure IG illustrates a step of removing the sacrificial layers 104 and 108, by selective etching of the layers 104 and 108 with respect to the other elements of the assembly. The removal of layers 104 and 108 is for example carried out by etching based on xenon di-fluoride (XeF2). Other etching methods can however be used, for example wet chemical etching, in which case a drying step can be provided at the end of the etching step, for example supercritical CO2 drying · During this step the etching of the layer 108 is carried out via the connection zones between the layer 104 and the layer 108 defined by the openings 107 in FIG. 1B. The etching of the sacrificial layers 104 and 108 leads to the release of the chips 150 and the breakable mechanical fasteners 120. It will be noted that according to the etching process used, a passivation of the flanks of the chips can be carried out before etching, to avoid the substrate of the chip is attacked during the etching of the sacrificial layers.
    At the end of this step, an assembly is obtained comprising a plurality of elementary chips 150 suspended above the upper face of the source substrate 100 by breakable mechanical fasteners 120. In this example, the upper protective layer 112 and the central portion of the layer 106 (the portion of the layer 106 situated, in top view, between the openings 107 formed in the layer 106 in the step described in relation to FIG. 1B) are considered to be part of the elementary chip 150. At this stage, only the breakable mechanical fasteners 120 connect the chip 150 to the source substrate 100. Each fastener 120 has a lower face fixed to the face
    B16534 - DD18354 upper of the source substrate 100 (via the lower protective layer 102 secured to the substrate 100 in this example) and an upper face fixed to the lower face of the chip 150. For each elementary chip 150, the surface fasteners 120 in contact with the underside of the chip is less than the total area of the underside of the chip, for example less than half of the total area of the underside of the chip, for example less than 20% of the total surface of the lower face of the chip, for example less than 5% of the total surface of the lower face of the chip. The rest of the surface of the lower face of the chip is separated from the upper face of the source substrate 100 by a region free of any solid material. In the example described above, each breakable mechanical fastener 120 is entirely located under (below) the chip 150 with which it is associated, which makes it possible to maximize the surface density of chips that can be provided on the face source substrate.
    Figure 2 is a perspective view illustrating the breakable mechanical fasteners 120 made by the method described above. For the sake of clarity, the chip 150 has not been shown in FIG. 2. As it appears in FIG. 2, each fastener 120 has, seen from above, the shape of a rectilinear strip, and, in cross section, a coated L shape, the vertical bar of the coated L having its free end fixed to the upper face of the source substrate 100 and the horizontal bar of the coated L having its free end fixed to the lower face of the chip 150.
    Note that the embodiments described are not limited to the example described above in which each chip is connected to the substrate by two breakable mechanical fasteners in the form of a straight strip (in top view). More generally, the number of fasteners can be different from two (at least one fastener). Alternatively, each chip can be connected to the substrate by four breakable mechanical fasteners respectively placed opposite four corners of the chip. In addition, the width of the horizontal part of the fasteners (width of the
    B16534 - DD18354 bands in the example in figure 2) can be variable. For example, in top view, the breakable mechanical fasteners can have a triangular shape, a V-shape (which can be favorable to a concentration of the stresses at the time of the tear-off which makes it easier to break the attachment), or any other suitable form.
    Figures 3A, 3B, 3C, 3D, 3E, 3F and 3G are sectional views illustrating steps of an example of another embodiment of a method of manufacturing a device for the transfer of chips d 'a source substrate on a destination substrate. More particularly, FIGS. 3A to 3G illustrate steps of a method of manufacturing a device comprising a source substrate 300, and a plurality of elementary chips 350, for example identical or similar, suspended above the upper face of the substrate 300, each chip 350 being connected to substrate 300 by at least one breakable mechanical fastener (a single fastener in the example of FIGS. 3A to 3G) connecting the upper face of the source substrate 300 to the lower face of chip 350. By for simplicity, only two chips 350, as well as the corresponding portion of the substrate 300, are represented in FIGS. 3A to 3G, it being understood that, in practice, a large number of chips 350 can be formed simultaneously on the upper face of the substrate 300.
    In this example, each elementary chip 350 comprises a stack of an LED based on a IIIV semiconductor material such as gallium nitride, and of a control circuit of the LED, for example a CMOS circuit. By way of example, the elementary chips 350 are chips of the type described in the French patent application No. 1561421 mentioned above. However, the embodiments described are not limited to this particular case. More generally, the method of FIGS. 3A to 3G can be adapted to any other type of semiconductor chips, for example chips comprising only one LED (without CMOS control circuit), chips comprising only one CMOS circuit, photovoltaic chips, etc. .
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    FIG. 3A illustrates a step of producing an assembly comprising a stack of a temporary support substrate 310, of a semiconductor substrate 320, for example made of silicon, in and on which a plurality of elementary control circuits 321 are formed corresponding respectively to the control circuits of the various elementary chips 350, and of a semiconductor substrate 330, for example of a III-V semiconductor material, for example of gallium nitride, in and on which are formed a plurality of LEDs 331 corresponding respectively to the LEDs of the various elementary chips 350. In this example, the underside of the semiconductor substrate
    320 rests on the upper face of the support substrate 310, and the lower face of the semiconductor substrate 330 rests on the upper face of the semiconductor substrate 320.
    By way of example, the substrate 320 is first transferred alone on the upper face of the support substrate 310, then treated to produce the elementary control circuits 321, for example in CMOS technology. Each elementary control circuit 321 comprises for example one or more transistors adapted to control the current and / or the voltage applied to the LED 331 of the chip. Each elementary control circuit 321 comprises, on the side of its face opposite to the support substrate 330, that is to say on the side of its upper face in the example shown, at least one electrical connection terminal of the circuit
    321 to LED 331.
    The substrate 330 can in turn be formed separately on a growth substrate (not shown), then treated to produce the elementary LEDs 331. The substrate 330 is then transferred to the upper face of the substrate 320 so as to connect each elementary LED 331 from the substrate 330 to the corresponding elementary control circuit 321 of the substrate 320. The growth substrate is then removed so as to obtain the stack shown in FIG. 3A. As a variant, the stack of semiconductor layers constituting the LEDs can be added to the substrate 320 before individualization of the elementary LEDs
    B16534 - DD18354
    331. The growth substrate of the stack of semiconductor layers constituting the LEDs is then removed to allow the individualization of the LEDs.
    At the end of the steps of FIG. 3A, the elementary chips 350 of the assembly are not yet individualized. The vertical broken lines in FIGS. 3A to 3E delimit the lateral edges of the future individual elementary chips.
    FIGS. 3B to 3D illustrate stages in the manufacture of breakable mechanical fasteners intended to connect the elementary chips 350 to the source substrate 300.
    FIG. 3B more particularly illustrates a step of depositing, on the upper face of the substrate 330, a lower anchoring layer 302, for example made of silicon oxide. The layer 302 is for example in contact with the upper face of the substrate 330. The layer 302 comprises through openings 303 opening onto the upper face of the substrate 330. In this example, for each elementary chip 350, the layer 302 comprises an opening 303 extending over the entire surface of the chip, except at a part of a peripheral region of the chip in which the layer 302 extends over the upper face of the chip. More particularly, in this example, for each elementary chip 350, the opening 303 extends over the entire surface of the chip except at a lateral edge of the chip, where a portion 302a of the layer 302 forms a tongue astride the edge of the chip, that is to say having a part of its lower surface in contact with the upper face of the chip and another part of its lower surface in contact with the upper face of the substrate 330 in a region of the substrate 330 external and adjacent to the chip. At at least one other part of the periphery of each chip, for example on the side of the lateral edge of the chip opposite to the region 302a, the opening 303 extends beyond the lateral edge of the chip. In other words, each opening 303 comprises a portion 303a extending, in top view, above a region of the substrate 330 external and adjacent to the chip. As
    B16534 - DD18354 for example, the layer 302 is first deposited continuously over the entire upper surface of the substrate 330, then removed locally by photolithography and etching to form the openings 303.
    FIG. 3C illustrates a step of depositing a sacrificial layer 304 on the upper face of the assembly obtained at the end of the steps of FIGS. 3A and 3B. Layer 304 is made of a material that can be etched selectively with respect to the material of layer 302. By way of example, layer 304 is made of polycrystalline silicon. More generally, any other suitable sacrificial material can be used, for example aluminum. The layer 304 extends in particular on and in contact with the upper face of the chips 350 at the bottom of the openings 303, and further extends on and in contact with the layer 302, outside the openings 303, and in particular on the portions 302a of the layer 302. The layer 304 comprises, for each chip 350, a through opening 305 opening onto the upper face of the tongue 302a of the layer 302 associated with the chip. In top view, the opening 305 is located outside of the chip 350 and at a distance from the lateral edge of the chip. By way of example, the layer 304 is first deposited continuously over the entire upper surface of the assembly obtained at the end of the steps of FIGS. 3A and 3B, then removed locally by photolithography and etching to form the openings 305.
    FIG. 3D illustrates a step of depositing, on the upper face of the assembly obtained at the end of the steps of FIGS. 3A, 3B and 3C, an upper anchoring layer 306 made of a material such as the sacrificial layer 304 is selectively etchable with respect to layers 302 and 306. By way of example, layer 306 is made of the same material as layer 302. In this example, layer 306 extends continuously over the entire upper surface of the assembly, that is to say on and in contact with the sacrificial layer 304 outside the openings 305 formed in the sacrificial layer in the previous step, and on and in contact with the lower anchoring layer 302 in the
    B16534 - DD18354 openings 305. The layer 306 is for example deposited over a thickness greater than that of the sacrificial layer 305 so as to completely fill the openings 305 previously formed in the sacrificial layer 304, then planarized, for example by chemical mechanical polishing (CMP). By way of example, at the end of the planarization step, a non-zero thickness of the layer 306 remains above the upper face of the sacrificial layer 304, for example a thickness of between 50 and 500 nm, for example between 100 and 200 nm.
    FIG. 3E illustrates a step of transferring the structure obtained at the end of the steps of FIGS. 3A to 3D on a support substrate 300, corresponding to the source substrate of the final device, then removal of the temporary support substrate 310. During this step, the face of the layer 306 opposite the substrates 330, 320 and 310 (that is to say the underside of the layer 306 in the orientation of FIG. 3E) is bonded, for example by molecular bonding, to one face (the upper face in the orientation of FIG. 3E) of the source substrate 300. The temporary substrate 310 is then removed, for example by grinding and chemical etching, so as to free access to the face of the substrate 320 opposite the substrate 330 (that is to say the upper face of the substrate 320 in the orientation of FIG. 3E).
    FIG. 3E further illustrates a step subsequent to the withdrawal of the substrate 310, making, on the upper face of the chips 350, terminals 342 for electrical connection of the chip 150 to an external device (two terminals 342 per chip in the example represented). By way of example, the terminals 342 are metal pads flush with the upper face of the chips 350. In the example shown, the upper face of the substrate 320 is coated with an insulating layer 341, for example made of silicon oxide, the metal pads 342 being arranged in openings formed in the insulating layer 341.
    FIG. 3E also illustrates an optional step of forming conductive microstructures 344 on the upper face of the electrical connection terminals 342, with a view to
    B16534 - DD18354 facilitate the subsequent attachment of the microchips to an external device, for example microtubes or microtips of the type described in relation to FIG. 1E.
    FIG. 3F illustrates a step of etching, from the upper face of the assembly obtained at the end of the steps of FIGS. 3A to 3E, trenches 370 for singularization of the elementary chips 350. More particularly, in the example shown, the trenches 370 extend vertically from the upper face of the assembly, pass entirely through the layer 341 and the substrates 320 and 330, and emerge on the upper face of the layer 302 (at the anchoring regions 302a) and the sacrificial layer 304 (at the level of the overflow regions 303a of the opening 303 in FIG. 3B). The trenches 370 are for example produced by reactive ion etching (RIE).
    FIG. 3G illustrates a step of removing the sacrificial layer 304, by selective etching of the layer 304 relative to the other elements of the assembly. The removal of layer 304 is for example carried out by etching based on xenon difluoride (XeF2) in the case of a sacrificial layer of polycrystalline silicon.
    At the end of this step, an assembly is obtained comprising a plurality of elementary chips 350 arranged on the upper face of the source substrate 300, each chip 350 comprising a stack of an LED 331 disposed on the source substrate 300, and of a control circuit 321 disposed on the side of the face of the LED 331 opposite the source substrate 300. In each chip, the LED 331 is electrically connected to the control circuit 321, and the control circuit 321 comprises, on its face opposite to the LEDs, terminals for connecting the chip to an external device. Each chip 350 is held suspended above the source substrate 300 by a breakable mechanical fastener formed by the region 302a of the layer 302 fixed to the underside of the chip. More particularly, each fastener 302a forms a tongue comprising:
    B16534 - DD18354
    a first region located under the chip 350, the upper face of which is fixed to the lower face of the chip and the lower face of which is separated from the upper face of the layer 306 by a region free of any solid material;
    - A second region opposite the first region, located, in top view, at a distance from the chip and from the first region, the lower face of which is fixed to the upper face of the layer 306; and
    a third intermediate region connecting the first region to the second region, the third region having its lower face separated from the upper face of the layer 306 by a layer free of any solid material.
    The rupture zone of each breakable mechanical fastener 302a corresponds to its third region, that is to say to the horizontal portion of the layer 302 situated between the region for fixing the tongue to the upper face of the layer 306 and the region of attachment of the tab to the underside of the chip. The energy to be applied to break the fasteners 302a can be controlled by adapting the dimensioning of the fasteners (and of the zones 304).
    Again, the embodiments described are not limited to the example described above in which each chip is connected to the substrate by two breakable mechanical fasteners in the form of a rectilinear strip (seen from above). More generally, the number of breakable mechanical fasteners can be different from two (at least one fastener) and the shape of the fasteners can be different from what has been described above.
    FIGS. 4A, 4B and 4C are sectional views illustrating steps of an example of an embodiment of a method for transferring chips from a source substrate to a destination substrate by means of a device produced by the method of FIGS. 3A to 3G, it being understood that a similar transfer method can be implemented using a device produced by the method of FIGS. 1A to 1G.
    B16534 - DD18354
    By way of example, the method of FIGS. 4A to 4C can be implemented during the manufacture of an emissive LED display device. In this example, the source substrate corresponds to the substrate 300 of the device of FIG. 3G, and the destination substrate 400 comprises a support plate or sheet 401 made of an insulating material, on which are arranged electrical connection elements, for example conductive tracks and tracks. The destination substrate 400 is for example a passive substrate, that is to say that it only comprises electrical connection elements for supplying the control and supply signals of the elementary chips 350 (corresponding to pixels of the display device). As a variant, the elementary chips of the device are simple LEDs, without an integrated control circuit, in which case the destination substrate 400 can be an active substrate, for example a CMOS circuit, integrating LED control circuits. The destination substrate 400 comprises a connection face, its upper face in the example shown, intended to receive the chips 350. For each chip of the final device, the destination substrate 400 comprises, on its connection face, a plurality of ranges of electrical connection 402 (one per electrical connection terminal of the chip) intended to be connected respectively to the electrical connection terminals of the chip.
    FIG. 4A illustrates a step during which, after having separately formed the chips 350 on the source substrate 300, and the destination substrate 400, the chips 350 are positioned opposite the corresponding transfer zones of the destination substrate 400, connection faces of the chips 350 facing the connection face of the substrate 400, using the source substrate 300 as a handle.
    For the sake of simplification of the figures, the chips 350 have not been detailed in FIGS. 4A to 4G. Only the electrical connection pads 342 of the chips are visible in these figures.
    B16534 - DD18354
    The chips 350, attached to the source substrate 300 by their LEDs 331 (FIG. 3G) via the breakable mechanical fasteners 302a (FIG. 3G), are brought opposite the corresponding reception areas of the destination substrate 400, connection faces turned. towards the connection face of the substrate 400.
    FIG. 4B illustrates a step during which the chips 350 are fixed on the destination substrate 400 and electrically connected to the destination substrate 400, by fixing and connection of the electrical connection pads 342 of the chips on the corresponding electrical connection pads 402 of the substrate 400. By way of example, the electrical connection pads 342 of the chips are coated with microtubes 344 as described in relation to FIG. 3G, and the corresponding electrical connection pads 402 of the substrate 400 are protruding. The assembly comprising the source substrate 300 and the chips 350 is then pressed against the destination substrate 400, connection faces of the chips 350 facing the connection face of the substrate 400. For each chip whose electrical connection pads 342 are facing each other with respect to electrical connection pads 402 of the substrate 400, the microtubes 344 of the chip penetrate into the corresponding electrical connection pads 402 of the substrate 400. The embodiments described are not however limited to this particular connection mode. Alternatively, the chips 350 may be fixed by direct bonding of the electrical connection pads 342 of the chips to the corresponding electrical connection pads 402 of the substrate 400, by soldering or soldering the pads 342 to the pads 402, or by any other suitable fixing method.
    FIG. 4G illustrates a step during which the source substrate 300 is removed, which leads to the breakage of the breakable mechanical fasteners connecting to the source substrate 300 the chips 350, now secured to the destination substrate.
    In practice, the pitch P300 of the chips on the source substrate 300, for example of the order of 10 to 50 μm, may be less than the pitch P400 of the final device after transfer to the substrate 400,
    B16534 - DD18354 for example between 15 pm and 1 mm, for example of the order of 100 to 500 pm.
    In the example described in relation to FIGS. 4A to 4C, the pitch P400 of the chips 400 on the destination substrate 400 is a multiple of the pitch P300 of the chips on the source substrate 300. By way of example, P4oq = N * P3oq, with N integer in the range from 1 to 10. Thus, provision is made to transfer only part of the chips 350 from the substrate 300 to the substrate 400, at the pitch of the substrate 400 (i.e. a chip on n with n = P400 / P300) 'then, if necessary, shift the substrate 300 with the remaining chips to transfer another part of the chips from the substrate 300 to the substrate 400, and so on until all the chips of the display device have been fixed on the destination substrate 400.
    At each iteration, the chips 350 are selectively detached from the source substrate 300. The source substrate 300 and the remaining chips 350 are then removed as illustrated in FIG. 4C.
    The provision of breakable mechanical fasteners connecting the chips 350 to the source substrate 300 makes it easy to selectively detach the chips 350 from the source substrate 300. In fact, when removing the source substrate 300, only the chips fixed to the destination substrate 400 are detached from the substrate source 300, by breaking their breakable mechanical attachments, the other chips remaining fixed to the source substrate due to the absence of connection between these chips and the destination substrate. Note that the provision, on the destination substrate side 400, of electrical connection pads protruding from the upper face of the substrate 400, makes it possible to facilitate the selective fixing of the chips on the destination substrate 400, and therefore the selective detachment of the chips from the source substrate 300 when removing the substrate 300.
    Compared to the transfer methods described in the above-mentioned international patent application WO2015 / 193435, an advantage of the method described in relation to FIGS. 4A to 4C is that the transfer is carried out directly from the source substrate
    B16534 - DD18354 to the destination substrate, without passing through an intermediate transfer substrate, which facilitates the implementation of the transfer.
    Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art. In particular, the embodiments described are not limited either to the examples of methods for manufacturing the breakable mechanical fasteners described in relation to FIGS. IA to IG and 3A to 3G, or to the examples of shapes of the breakable mechanical fasteners described in relation to the Figures IA to IG and 3A to 3G. More generally, the breakable mechanical fasteners can be produced by any process comprising alternating at least one step of depositing a permanent solid layer, for example made of silicon oxide, and at least one step of depositing a solid sacrificial layer, for example in polycrystalline silicon, or in a selectively etchable metal, for example in wet etching, compared to the other materials of the structure. The successive permanent and sacrificial solid layers may comprise openings, for example made by photolithography and etching, in particular to define the shape of the breakable mechanical fasteners and to allow the total removal of the sacrificial layer (s) once the chips are secured to the source substrate and individualized.
    It will also be noted that in a transfer device of the type described in relation to FIG. IG or 3G, due to the short distance separating each elementary chip from the source substrate, it may happen that the rear face of the chip (the lower face in the orientation of FIGS. IG and 3G) is pressed against the upper face of the source substrate, in particular when a vertical pressure is applied to the front face of the chip. In this case, to prevent the chip from remaining stuck, by molecular bonding, to the upper face of the source substrate, provision may be made to impart a certain roughness to the upper face of the source substrate (the upper face of the layer 102 in the example of figure IG or the upper side of the
    B16534 - DD18354 layer 306 in the example in Figure 3G), for example a roughness greater than 5 nm.
    In addition, the embodiments described are not limited to the examples of materials and dimensions mentioned in the present description.
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    1. Device for transferring chips from a source substrate to a destination substrate, comprising:
    a source substrate (100; 300) having a lower face and an upper face; and a plurality of elementary chips (150; 350) arranged on the upper face of the source substrate, in which each elementary chip (150; 350) is suspended above the source substrate (100; 300) by at least one breakable mechanical fastener (120; 302a), said at least one breakable mechanical fastener having a lower face fixed to the upper face of the source substrate (100; 300) and an upper face fixed to the lower face of the chip (150; 350).
    [2" id="c-fr-0002]
    2. Device according to claim 1, wherein, for each chip (150), said at least one breakable mechanical fastener (120) connecting the chip to the source substrate is located entirely under the chip.
    [3" id="c-fr-0003]
    3. Device according to claim 1, wherein, for each chip (350), said at least one breakable mechanical fastener (302a) connecting the chip to the source substrate is located partly only under the chip.
    [4" id="c-fr-0004]
    4. Device according to any one of claims 1 to 3, wherein, for each elementary chip (150; 350), only part of the underside of the chip is in contact with said at least one breakable mechanical fastener (120 ; 302a), the remaining part of the lower face of the chip being separated from the upper face of the source substrate (100; 300) by a region free of any solid material.
    [5" id="c-fr-0005]
    5. Device according to any one of claims 1 to 4, wherein each elementary chip (150; 350) comprises one or more electrical connection terminals (132; 342) to an external device arranged on the side of its face opposite to the substrate source (100; 300).
    [6" id="c-fr-0006]
    6. Device according to any one of claims 1 to 5, wherein each elementary chip (150) further comprises
    B16534 - DD18354 one or more electrical connection terminals to an external device arranged on the side of its face facing the source substrate (100; 300).
    [7" id="c-fr-0007]
    7. Device according to any one of claims 1 to 6, wherein the upper face of the source substrate (100; 300) has a surface roughness greater than 5 nm.
    [8" id="c-fr-0008]
    8. Device according to any one of claims 1 to 7, wherein each elementary chip (350) comprises an LED (331).
    [9" id="c-fr-0009]
    9. Device according to any one of claims 1 to 7, in which each elementary chip (350) comprises a stack of an LED (331) and of an elementary circuit (321) for controlling the LED, the elementary circuit control (321) being disposed on the side of the LED (331) opposite the source substrate (300).
    [10" id="c-fr-0010]
    10. Device according to any one of claims 1 to 7, in which each elementary chip (350) is a wavelength conversion element.
    [11" id="c-fr-0011]
    11. A method of manufacturing a device according to any one of claims 1 to 10, comprising the following successive steps:
    a) forming on the upper face of the source substrate (100) a first stack comprising an alternation of at least one permanent solid layer (102, 106, 112) and at least one sacrificial layer (104, 108) so as to define the breakable mechanical fasteners (120) of the device;
    b) adding on the upper face of the first stack a functional layer (130);
    c) forming singling trenches (140) crossing the functional layer (130) and delimiting the elementary chips (150) of the device; and
    d) etching said at least one sacrificial layer of the bonding stack without removing said at least one permanent solid layer.
    B16534 - DD18354
    [12" id="c-fr-0012]
    12. Method for manufacturing a device according to any one of claims 1 to 10, comprising the following successive steps:
    a) forming a functional layer (320, 330) on one side of a temporary support substrate (310);
    b) forming, on the face of the functional layer (320, 330) opposite the temporary support substrate (310), a bonding stack comprising an alternation of at least one permanent solid layer (302, 306) and at least at least one sacrificial layer (304) so as to define the breakable mechanical attachments (302a) of the device;
    c) attaching the assembly comprising the temporary support substrate (310), the functional layer (320, 330) and the bonding stack on the upper face of the source substrate (300), so that the temporary support substrate ( 310) is disposed on the side of the connecting stack opposite the source substrate (300), then remove the temporary support substrate (310);
    d) forming singling trenches (370) crossing the functional layer (320, 330) and delimiting the elementary chips (350) of the device; and
    e) etching said at least one sacrificial layer of the bonding stack without removing said at least one permanent solid layer.
    [13" id="c-fr-0013]
    13. The method of claim 11 or 12, wherein said at least one permanent solid layer (102, 106, 112; 302, 306) is made of silicon oxide, and wherein said at least one sacrificial layer (104, 108; 304) is made of polycrystalline silicon.
    [14" id="c-fr-0014]
    14. Method according to any one of claims 11 to 13, wherein the step of etching said at least one sacrificial layer of the bonding stack without removing said at least one permanent solid layer is carried out by etching based on di - xenon fluoride (XeF2).
    B16534 - DD18354
    [15" id="c-fr-0015]
    15. Method for transferring elementary chips (350) from a source substrate (300) onto a destination substrate (400) by means of a device according to any one of claims 1 to 10, comprising the following successive steps:
    positioning the elementary chips (350) vis-à-vis corresponding transfer zones of the destination substrate (400) using the source substrate (300) as a handle;
    fixing the elementary chips (350) on the destination substrate (400) by their face opposite to the source substrate (300); and moving the source substrate (300) away from the destination substrate so as to break the breakable mechanical fasteners connecting to the source substrate (300) the elementary chips (350) now secured to the destination substrate.
    [16" id="c-fr-0016]
    16. The method of claim 15, wherein the step of fixing the elementary chips (350) on the destination substrate (400) comprises the electrical connection of electrical connection terminals (342) previously formed on the face of the elementary chips (350 ) opposite the source substrate (300), to corresponding electrical connection terminals (402) of the destination substrate (400).
    [17" id="c-fr-0017]
    17. The method of claim 15 or 16, wherein the pitch (P300) of the elementary chips (350) on the source substrate (300) is less than the pitch (P400) of the elementary chips (350) on the destination substrate.
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    同族专利:
    公开号 | 公开日
    CN110634783A|2019-12-31|
    EP3598483B1|2020-09-23|
    FR3082998B1|2021-01-08|
    EP3598483A1|2020-01-22|
    US10923460B2|2021-02-16|
    US20190393201A1|2019-12-26|
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    法律状态:
    2019-06-28| PLFP| Fee payment|Year of fee payment: 2 |
    2019-12-27| PLSC| Search report ready|Effective date: 20191227 |
    2020-06-30| PLFP| Fee payment|Year of fee payment: 3 |
    2021-06-30| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1855672A|FR3082998B1|2018-06-25|2018-06-25|DEVICE AND METHODS FOR TRANSFERRING CHIPS FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATE|
    FR1855672|2018-06-25|FR1855672A| FR3082998B1|2018-06-25|2018-06-25|DEVICE AND METHODS FOR TRANSFERRING CHIPS FROM A SOURCE SUBSTRATE TO A DESTINATION SUBSTRATE|
    EP19181725.3A| EP3598483B1|2018-06-25|2019-06-21|Device and methods for transferring chips from a source substrate to a destination substrate|
    US16/450,557| US10923460B2|2018-06-25|2019-06-24|Device and methods for the transfer of chips from a source substrate onto a destination substrate|
    CN201910554589.2A| CN110634783A|2018-06-25|2019-06-25|Apparatus and method for transferring chips from source substrate to target substrate|
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